Exploring Independent Gates in FinFET-Based Transistor Network Generation.

Abstract

Firstly, this work presents an analysis pointing the impacts of the FinFET technology in the transistor network generation during the logic synthesis step. This analysis presents some case studies demonstrating that a new paradigm has been introduced by the double-gate devices, like the independent-gate (IG) FinFETs. Moreover, this work demonstrates that this new paradigm introduces a lack to be explored. Since the conventional methods for transistor network generation are not able to explore the potential provided by double-gate devices. Thus, this work proposes two alternative methods for IG FinFET-based transistor network generation. The first one is a graph-based method, which aims to find promising patterns to explore the potential provided by the double-gate devices. The second one aims to defactoring Boolean expression in order to maximize the use of the independent gates of each IG FinFET. The experiments have demonstrated that the proposed methods are able to generate optimized IG FinFET transistor networks, with a low cost in run time. Moreover, the obtained results demonstrate that, in fact, the conventional methods of transistor network generation are not the best alternative to design networks based in double-gate devices. This way, the results reinforce the existence of a new paradigm introduced by the IG FinFET technology. Finally, the analysis presented in this work provides support to design new methods to build transistor networks based in IG FinFETs.