Algoritmos e arquiteturas de hardware para a compressão de quadros de referência em codificadores de vídeo digitais

Abstract

Current video coding systems require a growing external memory bandwidth to encode a single video frame. This is happening because there is a large increase in the digital videos resolutions, as well as the new coding tools used by encoders. Among the main modules of the current video encoders, the module that performs more memory accesses is the Motion Estimation (ME). The ME requires a large memory bandwidth, which is mostly used for read and write the reference frames in the memory. This operation generates high energy consumption, since memory accesses are one of the main power demanding elements in current digital systems. This problem becomes more evident when battery-powered devices are considered. In this sense, this dissertation proposes algorithmic and architectural solutions for the reference frames compression before they are sent to memory. In this sense, this dissertation proposes algorithmic and architectural solutions for the reference frame compression before they are sent to memory. Thus, reducing the memory accesses and the memory bandwidth for the ME process. In this work, three solutions were developed: DRFC (Differential Reference Frame Coder), DRFVLC (Differential Reference Frame Variable-Length Coder), and the DDRFVLC (Double Differential Reference Frame Variable-Length Coder). All of these solutions follow the same operating flow, differential coding followed by entropy coding. The difference between them is the amount of differential coding used and the entropy coding. The solutions developed achieve high compression rates and high memory bandwidth reduction. These solutions achieve a compression ratio from 50% to 70%, outperforming any lossless reference frame compressor available in the current literature. The hardware architectures for the three algorithms, including the encoder and decoder modules, have been developed. These architectures were described in VHDL and synthesized for ASIC standard cells. The synthesis was done for technologies, 65nm and 180nm, and two operating frequencies, 62.5MHz and 250MHz. The architectures syntheses results shown that DDRFVLC is the most efficient solution, with a power dissipation of 1.13mW to encode HD 1080p videos, and 3.25mW to UHD 4K videos, which is a negligible overhead, since this solution reaches energy savings of 90.36mJ (65.14%) from the external memory access.