Análise da suscetibilidade de portas lógicas na presença de falhas de efeitos singulares

Abstract

To deal with the CMOS scaling problems, new design methodologies are necessary to improve the robustness of the circuits. Given the overheads associated with the traditional fault-tolerant approaches, alternative solutions, based on partial fault tolerance and fault avoidance, are also being considered as possible solutions to the reliability problem. In this context, an accurate evaluation of circuit’s reliability is fundamental, to allow a reliability-aware automated design flow, where the synthesis tool could rapidly cycle through several circuit configurations to assess the best option. In the circuit reliability evaluation, the interconection of the logic gates presented in the circuit is an important factor. Also, to evaluate the possible input combinations of a logic gate in the presence of faults a matrix is constantly used. In this matrix, called in this work as Representation Matrix for logic gates, they are used in the circuit reliability evaluation to represent the behavior of logic gates considering faults. In this way, this thesis proposes models capable of analyze logic gates susceptibility in different abstraction levels and generate representation matrices for these logic gates. For this analysis, three models are proposed based on transistor arrangement, stick diagram and layout of logic gates. An experiment was performed considering two different library cells, one considering transistor dimentions (45nm) and other considering regular layouts (15nm). The results for these library cells are used to analyze circuit reliability from eight circuis of ISCAS’85 benchmark. The results provided by this thesis shows an impact on the logic gates susceptibility when considering the design of these gates. Based on the results, the Mean Time Between Failures (MTBF) of the circuit reliability obtained by the generated matrices shown a considerable reduction. For both libraries, the generated matrices produced a reduction of 49% on the MTBF generated by the reliability evaluation when considering these matrices.