Desenvolvimento de hardware para a transformada rotacional 8x8 com foco na codificação de vídeos digitais de altíssima resolução

Abstract

The Rotational Transform (ROT) is one of the novel tools proposed for the HEVC emergent video coding standard. The main goal of this coding tool is to achieve higher energy compaction of the main transform coefficient matrix and thus improve entropy coding and minimize quantization error. Dedicated hardware architectures for video coding and decoding are essential to guarantee the necessary performance with low power and energy consumption, which are especially critical resources on portable and mobile devices. This work presents an investigation of the ROT focusing on the development of hardware solutions for the transform. The work explains in details the algorithmic exploration targeting hardware implementation. Three architectural versions are presented for the forward and inverse ROT transforms, generating different performance alternatives considering processing rate and hardware consumption. The architectures were described in VHDL and synthesized for a Stratix III FPGA. Results show that all versions of the architecture are capable of processing videos up to the resolution 4K UHD (3840x2160 pixels) at 30 frames per second. The version with the highest processing rate achieved a maximum operation frequency of 215.01 MHz. This version of the architecture reaches a processing rate of 1.72 billion samples per second, allowing it to process videos up to the resolution 8K UHD (7680x4320 pixels) at 30 frames per second.