An evaluation of memory controllers for non-volatile memories

Abstract

Many demands which include performance and energy consumption are present in current computational systems. In this context, actual memory technologies are critical components which affect directly both performance and energy cost of a system. Thus, memory needs improvements since they could be reaching its scalability limit. One of the alternatives to improve memory subsystems is the use of non-volatile memories (NVMs). These memories have overall low energy consumption and better scalability when comparing with volatile memories. However, NVMs still have issues which need to be overcome in order to allow large-scale use. Those issues include costly write operations (both on latency and energy) and lower material endurance if compared to current memory technologies. Parallel to that, one difficulty to adopt NVMs as main memories in computational systems is related to providing a proper scheduling of memory operations – as it should cope with the particular characteristics of NVMs. With that issues in mind, this work presents a memory controller implementation – in addition to that, a runtime analysis of memory operations in NVM-based systems is performed. To implement a memory controller, we use Gem5 and NVMain simulators, since their combination could reach runtime evaluations that this work aims. Then, the implemented controller was tested by running applications from MediaBench and MiBench benchmark set. With that, the controller was analyzed under different configurations. Tests were performed using the three most well-known and studied NVMs (PCRAM – Phase Change Random Access Memory, RRAM – Resistive Random Access Memory and STT-RAM – Spin Transfer Torque Random Access Memory). The main observations that could be highlighted in this work were: (i) while running the benchmarks in isolation, the time spent in serving memory requests is very low, not surpassing 2% of the total execution time of any application tested, (ii) when running the memory controller under different NVM technologies, latencies of read and write operations in overall were mostly impacted by the different type of memories used, (iii) when using queues with variable sizes to hold memory requests, it made negligible difference in overall performance, due to applications having small busy periods, i.e., generating and serving a small number of memory requests in detriment of other operations. Lastly, a comparison between the implemented memory controller and NVMain default memory controllers was performed, which pointed out that in the majority of the studied cases, the proposed memory controller may need extra techniques to get better performance.