Comparação de diferentes topologias de portas XOR em uma tecnologia de 45-nm

Abstract

Digital systems are present in most human activities, and an increasing number of people interact daily with a series of circuits in a wide range of equipments. The nanometric dimensions of the current integrated devices generate a series of challenges to be overcome, including the circuit optimization in order to have high performance and low consumption, filling increasingly stringent requirements to be suitable for use in high-performance portable systems. The XOR logic gates (Exclusive-OR) play a fundamental role for the functionality of various logic circuits and the project of high performance XOR logic gates, with noise immunity and low power consumption, consists in an important line of research in the ?eld of integrated circuits project. Based on the rules of the most used logic styles, CMOS and PTL, many XOR gates arrangements have been proposed. This paper presents an investigation into these arrangements and the techniques that underlie their design, as well as hybrid styles that have been proposed. There’s an evaluation of twenty-two XOR arrangements proposed in literature, with the results obtained from consumption and delay simulations for a 45-nm technology.