Desenvolvimento arquitetural para a predição intraquadro do padrão HEVC de codificação de vídeos

Abstract

Video coding is an essential area due to the increasing number of applications and devices that are able to handle high definition digital videos. The HEVC is the most recent and most efficient video coding standard created by the ITU-T VCEG and ISO/IEC MPEG groups, and its development was motivated by the increasing diversity of services and the emergence of beyond-HD formats such as UHD 4K (3840x2160 pixels) and UHD 8K (7680x4320 pixels). The intrapicture prediction is responsible to reduce spatial redundancy between samples inside the same frame. The HEVC standard defines several new techniques, which increase the intra prediction efficiency, but also increase its complexity. This work presents the development of hardware architectures for the HEVC intra prediction, considering different targets of compression efficiency, throughput, area cost, power dissipation and energetic efficiency. All designs were described in VHDL and synthesized using the NanGate 45 nm 0.95 v cell library. The main solution uses 4952K gates and, when running at a frequency of 529 MHz, it is able to process UHD 8K videos at 120 frames per second with a power dissipation of 363 mW and an energetic efficiency of 32.02 pJ/sample. When compared to related works, the developed architectures presented very competitive results.