Exploração no espaço de projeto de arquiteturas para os modos angulares da predição intra quadro do padrão VVC

Abstract

Today's society has a high demand for digital videos for various purposes in everyday life. Along with this demand, digital videos are increasingly having more information as their resolutions and frame rates per second increase. When we consider new technologies such as immersive videos, this amount of information can be exponentially greater. To meet this demand, video encoders are needed, responsible for compressing digital videos to sizes that can be stored and/or transmitted between devices with current market configurations. The Versatile Video Coding (VVC) encoder is one of the most current video encoders and was developed to provide greater coding efficiency than previously developed coding standards, in addition to enabling greater versatility for several different types of videos. In order for the standard to encode digital videos efficiently, VVC has several innovations in each of the basic tools of a video encoder. This dissertation proposes the creation of two heuristics and three hardware architectures for the angular modes tool of intra-frame prediction of the VVC coding standard. The objective of this work is to present different strategies focused on reducing computational cost and/or coding efficiency. Both heuristics presented focus on reducing the computational cost of the angular modes tool using strategies such as reducing angular modes and available block sizes. Two architectures created are based on the proposed heuristics, while the third architecture was created with a focus on not generating an impact on coding efficiency and, therefore, supports all modes and all block sizes defined for the tool in VVC. The results extracted from the heuristics show that the reductions in computational cost obtained, considering the entire VVC encoder, range from 18.72% to 60.92% of encoder time reduction. In order to reach these computational cost reduction values, the heuristics generated losses in coding efficiency that range from 2.17% to 8.62% of BD-Rate increase. In the synthesis results, the developed hardware architectures are capable of encoding videos at 1080p@30fps resolution with frequencies between 75.8 MHz and 131.3 MHz. The power dissipated for these frequencies was in the range of 91.65 mW and 755.18 mW, while the required area for each architecture was between 1,453 k gates and 13,508.4 k NAND2 gates.